This basic simulation shows a fundamental Von Neumann Architecture and I provide further description and details below the video.
The CPU is comprised of the Arithmetic Logic Unit (ALU) and Control Unit (CU), registers, buses, and we will see how it integrates with RAM. The simulation allows us to observe computer execution (Fetch, Decode, Execute) at the machine cycle level. Looking at the registers in further detail we see:
Registers used for control: Instruction Register (IR), Program Counter (PC), Index (X) and Stack Pointer (SP).
Registers for working with memory: Memory Address Register (MAR) that is used to access or determine RAM addresses and Memory Data Register (MDR) that is used to transfer content between the CPU and memory. Recall every byte in memory has both an address and contents.
Registers used for execution: Accumulator (ACC), Results (RES)
Flags Register used to show additional information resulting from execution (e.g. is result Zero or Negative, did a Carry or Overflow occur, etc.). The flags registers are used among other things to control execution through logical operations (think about your if-then-else statements in Programming & Logic).
Recall every architecture has a set of machine instructions (instruction set) and these are represented in binary (computer representation and encoding). Humans of course do not do well with binary so for our benefit, the simulation translates and represents the machine instructions and data in hexadecimal. We can observe the hexadecimal representation throughout the processing and this is also apparent if we look at the memory (RAM) by double clicking it once the simulation begins. You will note uninitialized memory is filled with 0’s however you should not rely on this or take this as the norm.
The simulator is programmed using a Register Transfer Language (RTL) that is a generic Assembly Language. Recall our presentation on computer hardware generations and my statement that there were equivalent generational advances in programming languages. Assembly Language was a step forward (2nd generation programming language) as it used acronyms or word stubs to represent each machine language instruction. With this basis we see there is a 1-to-1 relationship between Assembly Language and Machine Language and I think you will agree programming using RTL is much easier than machine language. Note the Assembly Language would need to get converted or translated into Machine Language to run and this is done by an Assembler.
From a top level perspective, the simulation will read in 2 numbers from the keyboard, sum the numbers and output them to the screen.
z = a + b
Now to accomplish this at the machine level the computer must read in the 1st number, store the number, read in the 2nd number, add this 2nd number to the stored 1st number and output the sum.
Note that it may take several machine cycles to perform a single instruction as the Fetch-Execute Cycle is actually: Fetch Instruction -> Increment PC (i.e. PC = PC + 1) -> Decode Instruction -> Execute Instruction. In the simulation, a single clock tick/cycle occurs every time we click run.
I now provide this algorithm in Assembly Language Instruction and in parenthesis the Machine Language Instruction (MLI) and a description prefaced by //. Note the Machine Language Instruction can be divided into 2 parts, the Operation or Opcode and the Operand (you have seen a similar convention in the Linux Labs with operations and options/arguments). As an example STA 63 is equivalent to and is translated into 2063 by the Assembler. In this instance, 20 is the Opcode for Store and 63 is an operand noting the it is a direct address hexadecimal address.
IN (MLI 5000) //Input number keyboard, Opcode is 50
STA 63 (MLI 2063) //Store in location 63, Opcode is 20, Arg is 63
IN (MLI 5000) //Input number keyboard
ADD 63 (MLI 3063) //Add to location 63, Opcode is 30, Arg is 63
OUT (MLI 6000) //Output, Opcode is 60
HALT (MLI 7000) //Halt, Opcode is 70
*It should be noted reading in a value is not as simple as the simulator presents above
What is the address size?
What is the bus width?
Here is the simulator I used in my video below but please note this link goes up and down quite frequently so I hope it is available when you attempt to access it. You may also have to right click to allow the Adobe Shockwave plugin and depending on your system you may even have to download shockwave.
If the link is down I copied the files below and the Adobe Shockwave file has the .dcr extension.
[listyofiles folder=”wp-content/uploads/FetchExecuteCycle” options=”table,filesize,icon”]
As always, please let me know if you have questions as your questions provide me with direction to further clarify, develop and present this topic.
Thank you again,